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simplifying system integration tm 78q8430 arm9(920t) embest evaluation board user manual may, 2008 rev. 1.0 um_8430_007 downloaded from: http:///
78q8430 arm9(920t) embest evaluation board user manual um_8430_007 2 rev. 1.0 ? 2008 teridian semiconductor corporation. all rights reserved. teridian semiconductor corporation is a registered trademark of teridian semiconductor corporation. simplifying system integration is a trademark of teridian semiconductor corporation. arm9 is a trademark of arm limited. linux is the registered trad emark of linus torvalds. pentium is a registered tradem ark of intel corporation. all other trademarks are the proper ty of their respective owners. teridian semiconductor corporation makes no warranty for the use of its products, other than expressly contained in the companys warranty detailed in the teridian semiconductor corporation standard terms and conditions. the company assumes no responsi bility for any errors which may appear in this document, reserves the right to change devices or sp ecifications detailed herein at any time without notice and does not make any commitment to update the information contained herein. accordingly, the reader is cautioned to verify that this document is current by comparing it to the latest version on http://www.teridian.com or by checking with your sales representative. teridian semiconductor corp., 6440 oak canyon, suite 100, irvine, ca 92618 tel (714) 508-8800, fax (714) 508-8877, http://www.teridian.com downloaded from: http:///
um_8430_007 78q8430 arm9(920t) embest evaluation board user manual rev. 1.0 3 table of contents 1 ? introduction ......................................................................................................................................... 5 ? 1.1 ? package contents ......................................................................................................................... 6 ? 1.2 ? safety and esd notes .................................................................................................................. 7 ? 1.3 ? system hardware requirements .................................................................................................. 7 ? 1.4 ? system software requirements ................................................................................................... 7 ? 2 ? system setup .............................................................................................................................. ........ 8 ? 2.1 ? jumper and dip switch settings ................................................................................................... 8 ? 2.2 ? connections .............................................................................................................................. .... 9 ? 2.3 ? system startup ........................................................................................................................... 10 ? 3 ? 78q8430 embest evaluation board schematic, bom and pcb layout ...................................... 11 ? 4 ? ordering information ........................................................................................................................ 20 ? 5 ? related documentation .................................................................................................................... 20 ? 6 ? contact information .......................................................................................................................... 20 ? downloaded from: http:///
78q8430 arm9(920t) embest evaluation board user manual um_8430_007 4 rev. 1.0 figures figure 1: 78q8430 system interface diagram ............................................................................................. 6 ? figure 2: 78q8430 embest evaluat ion board jumper locations ................................................................. 8 ? figure 3: 78q8430 embest evaluati on system hardware connections ...................................................... 9 ? figure 4: bus interface block diagram ....................................................................................................... 11 ? figure 5: bus interface schematic .............................................................................................................. 12 ? figure 6: mictor diagnostic connectors schematic ............................................................................... 13 ? figure 7: mac interface schematic ............................................................................................................ 14 ? figure 8: phy interface schematic ............................................................................................................. 15 ? figure 9: top silkscreen layout ................................................................................................................. 17 ? figure 10: top layer layout ....................................................................................................................... 17 ? figure 11: vcc layer layout ..................................................................................................................... 18 ? figure 12: ground layer layout ................................................................................................................. 18 ? figure 13: bottom layer layout .................................................................................................................. 19 ? figure 14: bottom silkscreen layout .......................................................................................................... 19 ? tables table 1: 78q8430 embest evaluation board jumper settings .................................................................... 8 ? table 2: 78q8430 embest evaluation board bill of materials .................................................................... 16 ? table 3: order number and part description ............................................................................................. 20 ? downloaded from: http:///
um_8430_007 78q8430 arm9(920t) embest evaluation board user manual rev. 1.0 5 1 introduction the 78q8430 embest evaluation board (d8430t3a_ eb) is a design example for a 10/100base-tx mac+phy embest s3ceb2410 daughter card. the d 8430t3a_eb plugs directly into the embest s3ceb2410 (arm9 ? based) motherboard. the network connection is provided by the 78q8430 which is a single chip auto-sensing, auto-switching (auto-ne gotiation or parallel detect modes and auto-mdix) 10/100base-tx fast ethernet transceiver with full du plex operation capability. the device is designed specifically for the audio/visual (a/v) and set top bo x (stb) markets and is easily interfaced to available a/v and stb core processors. the 78q8430 is compliant with applicable ieee-802.3 standards. mac and phy configuration and status registers are provided as specified by ieee802.3u. the integrated mac is supported by an internal 32kbyte transmit and receive sram fifo. the partition of transmit and receive queues is configurable through software, allowing the 78q8430 to be tuned for specific applications. the device contains hardware support for tcp-ip checksum and arc address recognition. the d8430t3a_eb provides support for the following 78q8430 hardware interface features: ? the system bus interface operates like external memory with an active low chip select. ? supports asynchronous big endian bus format. ? supports asynchronous 100 mhz operation. ? supports 32-bit wide data bus. ? optional eeprom interface for configuration data. ? two programmable led outputs for phy status. ? single +3.3v power supply voltage with a common ground plane. a host processor interfaces directly to the fifo via the global bus interface (gbi). the d8430t3a_eb is configured for 32-bit big endian bus format. figure 1 shows the 78q8430 system interfaces. downloaded from: http:///
78q8430 arm9(920t) embest evaluation board user manual um_8430_007 6 rev. 1.0 activity (programmable) 32-bit/16-bit/8-bit system bus interface configuration eeprom interface jtag interface 78q8430 single chip 10/100 ethernet mac & phy rj45 integrated rj-45 with 1:1 transformer cat5 cable led led link (programmable) figure 1: 78q8430 system interface diagram this document describes the setup and configuratio n of the 78q8430 embest evaluation board. the evaluation board requires operation with a +3.3 v power supply sourced from the embest bus interface on the s3ceb2410 evaluation board. the 78q8430 phy interfaces to a cat5 utp cable via a 1:1 transformer. the supplied software driver includes support for the linux ? operating system. the included 78q8430 software driver development guidelines and 78q8430 arm9 linux driver user and test guide documents describe the software interfacing requirement s for quick driver integration and prompt system evaluation of the 78q8430. use this document with those listed in the related documentation section. 1.1 package contents the 78q8430 embest evaluation board kit includes: ? a 78q8430 embest evaluation board (d8430t3a_eb). ? the embest arm9 s3ceb2410 evaluation platform. ? a memory card containing the 78q8430 linux software device driver and supporting tools. ? the following documents on cd: ? 78q8430 arm9(920t) embest evaluation b oard user manual (this document) ? 78q8430 preliminary data sheet ? 78q8430 layout guidelines ? 78q8430 software driver development guidelines ? 78q8430 78q8430 driver guide for arm920t linux ? 78q8430 arm9(920t) linux driver diagnostic guide the printed circuit board gerber files are available upon request. downloaded from: http:///
um_843 0_007 78q 8 rev. 1.0 1.2 s a connecti n boards. 1.3 s y the follo w system: ? the 7 ? the e ? a pc 1.4 s y the follo w evaluatio n ? 78q8 ? linux a fety and e n g live voltag e the evaluati these board s y stem har d w ing describe 7 8q8430 em b e mbest arm 9 to serve as t h y stem soft w w ing describe n board: 430 a rm li n operating sy e sd notes e s to the eval on boards ar e s ! d ware req u s the minimu b est evaluati o 9 s3ceb241 0 h e linux hos t w are req u s the minimu n ux 2.6.13 dri v s tem suppor t 8 430 a rm9( 9 uation syste m e esd sensit u irements m hardware r o n board (d8 4 0 evaluation p t and control t u irements m software r e v er, version 1 t ing kernel 2. 6 9 20t) embes t m will result i n ive! esd pr e r equirements 4 30t3a_eb) p latform. t he arm9 s 3 e quirements f .1. 6 .13. t evaluation b n potentially h e cautions mu s for the 78q8 . 3 ceb2410 pl a f or evaluatin g b oard user m h azardous vo l s t be taken w 430 embest a tform. g the 78q843 0 m anual l tages on the hen handling evaluation b o o ard 0 embest 7 downloaded from: http:///
78q8430 arm9(920t) embest evaluation board user manual um_8430_007 8 rev. 1.0 2 system setup 2.1 jumper and dip switch settings the 78q8430 embest evaluation board utilizes several jumpers (ja, jc and j12 through j15) for establishing the startup configur ation of the 78q8430 device. figure 2 shows the location of the jumpers. table 1 describes the jumper options. the jumper numbers and settings are printed on the board. figure 2: 78q8430 embest evaluation board jumper locations table 1: 78q8430 embest evaluation board jumper settings jumper name setting description j15 clkmode selection gnd internal clock. 3p3v external clock (default). ja chip select source cs0 selects the source for the 78q8430 chip select signal. the default setting is cs5. cs1 cs2 cs3 cs4 cs5 j12 j13 j14 interrupt selection int5 selects the destination for the 78q8430 interrupt signal. the default setting is int16. int6 int7 int8 int9 int16 int17 int18 downloaded from: http:///
um_8430_007 78q8430 arm9(920t) embest evaluation board user manual rev. 1.0 9 jumper name setting description jc clock source clk1 selects t he source for the 78q8430 clock. the default setting is cclk. clk0 vclk sclk cclk 2.2 connections connect the system components as shown in figure 3 . refer to the embest s3ceb2410 documentation for additional information on the connections for that platform. figure 3: 78q8430 embest evaluation system hardware connections step 1: attach the 78q8430 embest evaluation board to the s3ceb2410 evaluation board via the three connectors on the bottom of the 78q8430 evaluation board. step 2: connect the 78q8430 embest evaluation board ethernet port to the linux pc using a cat-5 cable. step 3: connect a serial console cable from the linux host pc serial port to the s3ceb2410 board serial port. step 4: insert the memory card containing the 78q8430 linux software device driver into the memory card slot on the s3ceb2410 board. downloaded from: http:///
78q8430 arm9(920t) embest evaluation board user manual um_8430_007 10 rev. 1.0 2.3 system startup step 1: on the linux host, set the testing port ip ad dress to 192.168.10.100 (the s3ceb2410 platform boots with ip address 192.168.10.99). step 2: open a full height xterm or kconsole window on the linux host. step 3: start minicom on the linux host at the xterm/kconsole command prompt: ~# minicom step 4: turn on the s3ceb2410 board power. refer to the s3ceb2410 documentation for additional information. the 78q8430 embest evaluation board receives its power through the embest bus interface on the s3ceb2410 evaluation board. step 5: boot the s3ceb2410 board. console messages must appear in the minicom window after power on. ? hit the space bar at the first boot prompt ? respond with: cpu set 200 2 ? on the next prompt, respond: boot step 6: when boot up completes, enter the following at the prompt: arp -s 192.168.10.100 00:0e:2e:5b:25:86 step 7: on the linux host, issue the following ping co mmand to verify the connection to the target: ping 192.168.10.99 downloaded from: http:///
um_8430_007 78q8430 arm9(920t) embest evaluation board user manual rev. 1.0 11 3 78q8430 embest evaluation board schematic, bom and pcb layout endian0 pmebbootsz1 bootsz0 waitmode tdi tdo tms trst tclk endian1 txp led1 led0 j1 xtlnxtlp rxn rxp txn j2rj45 25mhz crystal logic analyzer pods mictor connectors tp2 & tp5 promcs promclk promdi promdo vdclk clk1sdclk cdclk ngcs3 ngcs2ngcs5 ngcs4 r42 bint6 bint5 u4 bint9 bint8 bint7 bint17 bint16 bint19 bint18 r43 jc clkmode busmode interface s3ceb2410 clk0db31:0 ab9:0 bnwe bnoe ngcs1 ngcs0 nresetmemwait jp j12-j14 vcc33 l1 78q8430b data31:0 addr9:0 wrb oeb csb resetb busclkintb memwait ja vcca vccd figure 4: bus interface block diagram downloaded from: http:///
78q8430 arm9(920t) embest evaluation board user manual um_8430_007 12 rev. 1.0 figure 5: bus interface schematic 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 34 34 35 35 36 36 37 37 38 38 39 39 40 40 41 41 42 42 43 43 44 44 45 45 46 46 47 47 48 48 49 49 50 50 51 51 52 52 53 53 54 54 55 55 56 56 57 57 58 58 59 59 60 60 61 61 62 62 63 63 64 64 65 65 66 66 67 67 68 68 69 69 70 70 71 71 72 72 73 73 74 74 75 75 76 76 77 77 78 78 79 79 80 80 jp3pin header 40x2 ebs40x2 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 34 34 35 35 36 36 37 37 38 38 39 39 40 40 41 41 42 42 43 43 44 44 45 45 46 46 47 47 48 48 49 49 50 50 51 51 52 52 53 53 54 54 55 55 56 56 57 57 58 58 59 59 60 60 61 61 62 62 63 63 64 64 65 65 66 66 67 67 68 68 69 69 70 70 71 71 72 72 73 73 74 74 75 75 76 76 77 77 78 78 79 79 80 80 jp1pin header 40x2 ebs40x2 gnd gnd 3p3v (j302) 3p3v (j301) vclkp gnd 3p3v 3p3v 3p3v milmax 852-10-80-10-001 ngcs5 bnwe bnoe nreset ngcs0 ngcs2 ngcs4 mouser 575-002101 (2x50 pins) mount solder side ngcs[5:0] ngcs1 ngcs3 db17 db19 db21 db23 db27 db29 db25 db31 db3 db1 db6 db8 db4 db12 db14 db2 db10 db0 db7 db5 db11 db13 db9 db15 db30 db28 db24 db26 db22 db16 db18 db20 db[31:0] ab6 ab2 ab4 ab8 csb ab7 ab5 ab9 1.27x1.27 st hdr memwait nreset 1 2 3 4 j12 con4 bnwe bnoe 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15 16 16 17 17 18 18 19 19 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 34 34 35 35 36 36 37 37 38 38 39 39 40 40 41 41 42 42 43 43 44 44 45 45 46 46 47 47 48 48 49 49 50 50 51 51 52 52 53 53 54 54 55 55 56 56 57 57 58 58 59 59 60 60 61 61 62 62 63 63 64 64 65 65 66 66 67 67 68 68 69 69 70 70 71 71 72 72 73 73 74 74 75 75 76 76 77 77 78 78 79 79 80 80 jp2pin header 40x2 ebs40x2 r733 0603 r633 0603 1 2 3 4 j13 con4 clk0 clk1 ab3 1 2 3 jc3con3 1 2 3 jc1con3 ab[9:0] sdclk cdclk (j307) 1 2 3 4 j14 con4 cclk sclk 3p3v 3p3v 3p3v gnd memwait r333 0603 r533 0603 clkout1 bint18 bint16 bint6 gnd bint7 bint5 bint9 bint17 bint8 r433 0603 clkout0 1 gnd1 1 2 3 jc2con3 busclk intrb bint5 bint6 ab0 bint7 bint8 ab1 c410 0805 gnd 3p3v 3p3v vclk bint17 bint16 bint9 bint18 gnd 1 gnd2 busclk ngcs1 csb ngcs4 ngcs2 ngcs5 ngcs3 ngcs0 ab[9:0] db[31:0] 1 2 3 ja3con3 1 2 3 ja2con3 1 2 3 ja1con3 intrb c210 0805 gnd c310 0805 gnd downloaded from: http:///
um_8430_007 78q8430 arm9(920t) embest evaluation board user manual rev. 1.0 13 figure 6: mictor diagnostic connectors schematic 1 1 tp3 nc 1 gnd 3 clke 5 d15e 7 d14e 9 d13e 11 d12e 13 d11e 15 d10e 17 d9e 19 d8e 21 d7e 23 d6e 25 d5e 27 d4e 29 d3e 31 d2e 33 d1e 35 d0e 37 nc 2 nc 4 clko 6 d15o 8 d14o 10 d13o 12 d12o 14 d11o 16 d10o 18 d9o 20 d8o 22 d7o 24 d6o 26 d5o 28 d4o 30 d3o 32 d2o 34 d1o 36 d0o 38 gnd 39 gnd 40 gnd 41 gnd 42 gnd 43 tp2 mictor 38 pin connector nc 1 gnd 3 clke 5 d15e 7 d14e 9 d13e 11 d12e 13 d11e 15 d10e 17 d9e 19 d8e 21 d7e 23 d6e 25 d5e 27 d4e 29 d3e 31 d2e 33 d1e 35 d0e 37 nc 2 nc 4 clko 6 d15o 8 d14o 10 d13o 12 d12o 14 d11o 16 d10o 18 d9o 20 d8o 22 d7o 24 d6o 26 d5o 28 d4o 30 d3o 32 d2o 34 d1o 36 d0o 38 gnd 39 gnd 40 gnd 41 gnd 42 gnd 43 tp5 mictor 38 pin connector 1 1 tp6 busclk memwait intrb pmeb nreset csb bnwe bnoe ab[9:0] db[31:0] ab[9:0] gnd 2-767004-2 2-767004-2amp amp db28 (lsb) db13 db11 db18 db26 db25 db27 db29 db17 db4 db24 db15 db12 db9 db7 db23 db22 db8 db21 db3 (msb) db6 db5 db1 db30 db0 db20 db2 db19 db31 db14 db10 db16 ab4 ab5 bnwe ab7 busclk ab8 ab9 bnoe nreset ab6 ab2 csb ab3 memwait pmeb intrb ab1 ab0 tp26 tp55 db[31:0] gnd gnd downloaded from: http:///
78q8430 arm9(920t) embest evaluation board user manual um_8430_007 14 rev. 1.0 figure 7: mac interface schematic r381k 0603 r4333 0603 gnd gnd gnd gnd gnd gnd gnd gnd bnoe bnwe vcc 8 gnd 5 clk 2 cs 1 di 3 do 4 nc1 7 nc2 6 u493lc46b soic8 3p3v gnd promclk promdi db14 intb db3 db12 promcs db4 db7 db1 promdo db13 db15 db9 db2 r5610k 0603 db5 db6 db8 db0 db10 db[31:0] db11 busclk (lsb) intrb db[31:0] gnd pmeb memwait r4233 0603 3p3v r52 33 tdi csb csb r53 33 3p3v r551k 0603 data0 28 data1 29 data2 30 data3 31 data4 32 data5 33 data6 38 data7 39 data8 40 data9 41 data10 42 data11 45 data12 46 data13 47 data14 48 data15 49 data16 52 data17 53 data18 54 data19 55 data20 56 data21 57 data22 58 data23 59 data24 62 data25 63 data26 64 data27 65 data28 66 data29 67 data30 68 data31 69 intb 72 pmeb 73 memwait 13 addr2 18 addr3 19 addr4 20 addr5 21 addr6 22 addr7 23 addr8 24 addr9 25 addr0 10 addr1 9 busclk 15 resetb 7 csb 16 wrb 11 oeb 12 endian0 79 endian1 80 busmode 83 waitmode 84 clkmode 85 bootsz1 100 bootsz0 1 promclk 74 promcs 75 promdo 76 promdi 77 tclk 6 trst 5 tms 3 tdo 81 tdi 4 gnd1 2 gnd2 14 gnd3 34 gnd4 35 gnd5 26 gnd6 43 gnd7 50 gnd8 60 gnd9 70 gnd11 78 vcc1 8 vcc2 17 vcc3 36 vcc4 27 vcc5 37 vcc6 44 vcc7 51 vcc8 71 vcc9 61 vcc11 82 u2a78q8430b-100 tdo busclk r54 33 r57 33 1 2 3 j15 con3 r371k 0603 c100.1 0603 c110.1 0603 c120.1 0603 c510 0805 c90.1 0603 c610 0805 c80.1 0603 c70.1 0603 intrb r13 33 0603 3p3v db16 r11 33 0603 r22 33 0603 db30 db25 r15 33 0603 r17 33 0603 db21 db23 r12 33 0603 r9 33 0603 r14 33 0603 3p3v db18 r8 33 0603 memwait db24 db28 db17 r20 33 0603 r10 33 0603 r23 33 0603 (msb) bnoe bnwe nreset r18 33 0603 r21 33 0603 tms db22 r19 33 0603 db31 db26 r16 33 0603 db27 db29 db19 db20 r58 33 ab6 ab0 ab7 ab9 ab3 ab2 ab5 ab8 ab4 ab[9:0] ab[9:0] ab1 trst r59 33 nreset 3p3v r60 33 tclk r61 33 r24 33 0603 r25 33 0603 r27 33 0603 r26 33 0603 r28 33 0603 r29 33 0603 r31 33 0603 r30 33 0603 r62 33 gnd 1 2 3 4 5 6 7 8 9 10 j1con10 r32 33 0603 r33 33 0603 tms trst tdi tclk r35 33 0603 tdo r34 33 0603 gnd r4410k 0603 r4510k 0603 r36 33 0603 r39 33 0603 r41 33 0603 r40 33 0603 data29 data31 data30 data28 data25 data26 data22 data27 data23 data24 data18 data19 data17 data21 data20 data15 data13 data16 data14 data12 data11 data6 data9 data7 data10 data8 data5 data2 data1 data4 data3 data0 r63 33 r64 33 r65 33 3p3v r66 33 pmeb downloaded from: http:///
um_8430_007 78q8430 arm9(920t) embest evaluation board user manual rev. 1.0 15 figure 8: phy interface schematic cgnd xtln xtlp gnd gnd txp 97 txn 98 rxp 94 rxn 93 xtlp 87 xtln 88 vcca1 86 vcca2 95 vcca3 96 gnda1 89 gnda2 91 gnda3 99 led1 92 led0 90 u2b78q8430b-100 gnd active link rx/txlink gnd pins 2 and 4 pulse engr txop txon use zero ohm resistor gnd gnd rxip rxin cgnd c1310 0805 vcca gnd r51680 0603 r46680 0603 r4949.9 1%0603 c1927pf 0603 1 3 y1 25.000mhz 50ppmraltron l11b r5049.9 1%0603 c1710 0805 r4749.9 1%0603 l1 ferrite r_0805 c160.1 0603 c1827pf 0603 r4849.9 1%0603 c150.1 0603 c140.1 0603 3p3v 3p3v 3p3v gnd 3p3v gnd 8 1 2 3 4 5 6 7 13 14 9 10 11 12 23 24 raled rcled td+td- tdct cgnd1 cgnd2 rdct rd+ rd- lcledlaled cgnd3cgnd4 j2 j0011f01p tabup downloaded from: http:///
78q8430 arm9(920t) embest evaluation board user manual um_8430_007 16 rev. 1.0 table 2: 78q8430 embest evaluation board bill of materials item quantity reference part pcb footprint part number vendor 1 2 c18,c19 cap., 27pf, 50v c_0603 c1608c0g1h270j tdk 2 9 c7-c12,c14-c16 cap., 0.1uf, 16v c_0603 ecj-1vb1e104k panasonic 3 7 c2-c6,c13,c17 cap.,10uf,10v c_0805 grm21br61a106 ke19l murata 4 2 tp3,tp6 con1 testpoint 5011 keystone 5 7 ja1-ja3,jc1-jc3, j15 sip3 sip\3p pbc03saan sullins electronics corp 6 3 j12,j13,j14 sip4 sip\4p pbc04saan sullins electronics corp 7 1 j1 con10 sip\10p pbc10saan sullins electronics corp 8 3 jp1-jp3 40-pin header ebs40x2 852-10-100-10- 001000 mill max 9 1 j2 integrated rj45 rj45-int j1011f01p pulse eng 10 1 y1 25mhz crystal xtal-smd abmm-25mhz abracon 11 1 l1 ferrite bead l_0805 mmz2012s181a tdk 12 3 r44,r45,r56 res, 10k, 5% r_0603 erj-3geyj103v panasonic 13 3 r37,r38,r55 res, 1k, 1% r_0603 erj-eekf1001v panasonic 14 4 r47-r50 res, 49.9, 1% r_0603 erj-3ekf49r9v panasonic 15 52 r3-r36,r39-r43, r52,r53,r54, r57-r66 res, 33, 5% r_0603 erj-3geyj330v panasonic 16 2 r46,r51 res, 680, 5% r_0603 erj-3geyj681v panasonic 17 2 tp2,tp5 mictor 38-pin mictor 2-767004-2 tyco 18 1 l1 ferrite bead l_0805 mmz2012s181a tdk 19 1 u2 78q8430 100 lqfp 78q8430 teridian semiconductor 20 1 u4 93lc46 soic8 93lc46bt-i/sn microchip downloaded from: http:///
um_8430_007 78q8430 arm9(920t) embest evaluation board user manual rev. 1.0 17 figure 9: top silkscreen layout figure 10: top layer layout downloaded from: http:///
78q8430 arm9(920t) embest evaluation board user manual um_8430_007 18 rev. 1.0 figure 11: vcc layer layout figure 12: ground layer layout downloaded from: http:///
um_8430_007 78q8430 arm9(920t) embest evaluation board user manual rev. 1.0 19 figure 13: bottom layer layout figure 14: bottom silkscreen layout downloaded from: http:///
78q8430 arm9(920t) embest evaluation board user manual um_8430_007 20 rev. 1.0 4 ordering information table 3 lists the order number for the 78q8430 embest evaluation board. table 3: order number and part description part description order number 78q8430 embest evaluation board (d8430t3a_eb) evm8430-arm9 5 related documentation the following 78q8430 documents are available from teridian semiconductor corporation: 78q8430 preliminary data sheet 78q8430 layout guidelines 78q8430 software driver development guidelines 78q8430 driver guide for st 5100/os-20 with nexgen tcp/ip stack 78q8430 stem demo board user manual 78q8430 driver guide for arm920t linux 78q8430 arm9(920t) embest evaluation board user manual 78q8430 arm9(920t) linux driver diagnostic guide 6 contact information for more information about teridian semiconductor products or to check the availability of the 78q8430, contact us at: 6440 oak canyon road suite 100 irvine, ca 92618-5201 telephone: (714) 508-8800 fax: (714) 508-8878 email: lan.support@teridian.com for a complete list of worldwide sales offices, go to http://www.teridian.com . downloaded from: http:///
um_8430_007 78q8430 arm9(920t) embest evaluation board user manual rev. 1.0 21 revision history revision date description 1.0 may 6, 2008 first publication downloaded from: http:///

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